verilog2vhdl

verilog2vhdl is an utility that has been developed for those who wants to convert an existing verilog design into VHDL. The generated VHDL may not work as is and may require some manual correction to ensure the VHDL data type matching. This has been developed in Java( 1.6.x ) in order to make it platform independent and bundled as an executable JAR file. Click here to download this free translator for Linux platform and click here to download it for Windows.

Usage:

verilog2vhdl -in simple_and.v -top simple_and_top -out simple_and.vhd

OR

java -jar $EDAUTILS_ROOT/lib/verilog2vhdl.jar -in simple_and.v -top simple_and -out output.vhd

There are other switches like -only_entity to create just the entity correspomding to the specified top. Similarly, there is -only_component to create a component declaration corresponding to the specified module.

Requirements:

• Java 2 Standard Edition Runtime Environment