Scheture

Scheture project is our schematic capture package. The package is built atop the same database as all of the other Stabie-Soft products. The schematic editor handles iterated instances, bus'ed pins and wires, parameter passing etc.

The latest production version of Scheture is 3.3.1, please download it if your using an older version to get the latest updates and bug fixes.

Perhaps one of the best features is scheture's ability to generate a schematic (and symbols) from netlist formats such as verilog or spice. Take it for a 30 day test drive and see if it is right for you. See the pricing page for details on our free 30 day evaluations.

Features:

• User control of all object colors and fonts.
• Control of position, size, font, color of property display of symbols.
• A specific placement of a symbol may override property display position, size, font or color.
• Implicit connection of symbol pins by name possible for specific schematics.
• In the schematic here, note the bulk connections are made with this type of connection. No explicit connection to the bulk is drawn, but all unconnected bulks will be connected by name in this schematic only.
• Implicit global connection of symbol pins possible.
• Symbol properties may be set for display only (IE ignored by netlister).
• Symbol generator.
• Net tracing thru the hierarchy.
• Property values "push" down so in context display of properties available.
• Extractor.
• Hierarchical verilog out.
• Hierarchical spice out.
• Hierarchical smash out. (For Dolphin's SMASH mixed mode simulator).
• Netlist to schematic generator to build a schematic from a netlist.
• Sample of nor3 and adder. Both these schematics were built completely automatically from spice netlists. Note verilog can also be auto generated for cross probing or visualization of hdl.
• Parasitic net schematic generator to visualize an extracted net's R/C network.
• Interfaces with Mentor's RVE product. Cross-probe between layout & schematic.
• Interfaces to open source waveform viewer GWave.
• User specified port order available for spice subcircuits and verilog primitives.
• Plotting, and includes a command to plot all schematics in a library.
• Sample library of symbols provided.
• Free upgrades after purchase

What is new in this release:

• Generation of PDF files for a schematic, schematic hierarchy, or whole library. If the symbol's schematic is included in the same PDF, then symbol placements are linked to the schematic within the file for easy navigation. A simple example.
• A new keypoint mode was added so commands initiated thru a hot key press can have their first point entered if needed at the location of the key press.
• Reference libraries can be tcl expressions allowing symbol libraries to be moved easily.
• New ECL transistor placer algorithm in schematic generation from netlist.

What is new in version 3.3.7:

• This release adds a fast formless command to update wire, pin, and symbol names directly on the screen.
• The new command can modify symbol parameter values such as W/L too.
• After invoking the new command, simply click on the name or parameter value.
• A cursor is displayed on the window, and you can start typing.
• Keys such as arrows and delete move the cursor displayed on the screen.
• This is simpler and quicker to use than the existing form-based interface to change these values.