Dolphin Smash

Dolphin Smash is a free mixed-signal and multi-language simulator for PCB and IC designs. It extends its capabilities for mixed signal sensitivity-analysis and code-coverage, in order to identify circuit weaknesses for the DfM conscious designer and to detect flaws in Virtual Testbenches.

What is new in this release:

• This version improves the loading runtime of large Verilog files with an important number of ports and implements support of the .malias directive to assign an alias to a model or sub-circuit name, along with a number of minor corrections.

What is new in version 5.19.0:

• This version implements major improvements to instantiation of behavioral models (HDL/HDL-AMS) in SPICE netlists with mixed macro-models, better multi-threading capabilities to increase transient simulation speed of analog designs, Monte Carlo and Sweep analyses on logic designs, a domain coloring viewer with phase and magnitude viewing, .MODEL for Verilog-A foundry models, .NRT for equivalence checking between waveforms, and the ability to define a directory to redirect all output files.

What is new in version 5.18.0:

• This version implements major improvements among which domain coloring for a first approximation of the pole/zero locations, a .PZ directive for pole/zero analysis, support of .wav files as ouput of logic designs, and CCS segmentation extraction processing functions.

What is new in version 5.17.0:

• This version implements major improvements including extended Assertion-Based Verification (ABV) capabilities with SystemVerilog Assertions (SVA), compliance with Verilog-AMS wreal for Real Valued Modeling (RVM), increased Verilog-HDL and Verilog-A language compliance, improved HSpice compatibility with .IF,.ELSIF,.ELSE,.ENDIF conditional generate statements, and accelerated circuit loading, Monte Carlo and Sweep analysis.

What is new in version 5.16.2:

• This version delivers a significant speed increase for the loading of SPICE library files and circuits, particularly significant when accessing files on slow network disks.
• A number of minor enhancements and fixes were also made.

What is new in version 5.15.2:

• A number of defects were corrected and some minor improvements were implemented.

What is new in version 5.15.1:

• SMASH - Viewer:
• Enhancements:
• Added a menu to 'fold all' and 'unfold all' items in the text editor (DDIsa05778 - SMASH 5.15.0).
• Added an option in the "Add traces" dialog allowing to trace logic vectors as unsigned values in analog graphs (DDIsa05953 - SMASH 5.15.0).
• Added right-click menu entry in the circuit panel allowing to remove recent circuits (DDIsa05981 - SMASH 5.15.0).
• Added menu entries to show/hide left and bottom panes which could previously only be done by double-clicking on the
• splitters (DDIsa06032 - SMASH 5.15.1).
• Implemented exporting of the application setup to the circuit directory and editing of circuit configuration with the preferences dialog (DDIsa06034 - SMASH 5.15.1).
• Implemented the possibility to associate a Tcl script with a circuit to register circuit specific hook functions (DDIsa06098 - SMASH 5.15.1).
• Improved handling of simulator control file updates so that the original file is not damaged when there is no space left on
• disk (DDIsa06209 - SMASH 5.15.1).
• Modifications:
• Modified handling of FFT dialog to allowing specification of a negative time (DDIsa04663 - SMASH 5.15.0).
• Modified SMASH embedded Wine build under Linux to remove numerous Xlib error messages issued when running
• displayed on a Cygwin X server (DDIsa05532 - SMASH 5.15.0).
• Implemented a default temperature equal to 25 degC when the HSPICE flavor is selected (DDIsa05790 - SMASH 5.15.0).
• Modified generation of operating-point file so that logic related data is not output by default and can be enabled through
• the application preferences (DDIsa05154 - SMASH 5.15.1).
• Modified the 'OP' parameter of directives '.AC' and '.NOISE' which should have the same default value (DDIsa06037 - SMASH 5.15.1).
• Corrected embeddedWinelib to allow loading files with very long path names under Linux (DDIsa06193 - SMASH 5.15.1).
• Bug fixing:
• Corrected Wine version of SMASH in order to be able to load circuits requiring more than 600 Mb of allocated memory(DDIsa05525 - SMASH 5.15.0).
• Corrected the displaying of internal VHDL-AMS quantities in the add trace dialog (DDIsa06096 - SMASH 5.15.1).
• Corrected handling of the '.TRACE' directive which should not be case sensitive on waveform 'ONOISE' during a noise analysis (DDIsa06106 - SMASH 5.15.1).
• Corrected exporting of audio files from the "Audio File..." dialog which was aborting with an error message (DDIsa06117 - SMASH 5.15.1).
• Corrected SNR & THD computations when performed in a generic window from .FFT results file (DDIsa06192 - SMASH 5.15.1).
• Corrected handling of FFT waveforms from *.fft.amf in generic windows so that they are clamped at -400dB instead of -300dB (DDIsa06240 - SMASH 5.15.1).
• Corrected handling of update check which could cause SMASH to crash in presence of an empty change entry (DDIsa06242 - SMASH 5.15.1).
• Corrected waveform superposing which was disabled for logic simulations (DDIsa06258 - SMASH 5.15.1).
• Corrected the display of values in Tera (DDIsa06264 - SMASH 5.15.1).
• SMASH - Batch:
• Enhancements:
• Implemented the possibility to associate a Tcl script with a circuit to register circuit specific hook functions (DDIsa06098 - SMASH 5.15.1).
• Modifications
• Corrected embeddedWinelib to allow loading files with very long path names under Linux (DDIsa06193 - SMASH 5.15.1).
• Bug fixing:
• Corrected Wine version of SMASH in order to be able to load circuits requiring more than 600 Mb of allocated memory (DDIsa05525 - SMASH 5.15.0).
• SMASH - Kernel
• Enhancements:
• Implemented support of directive '.OPTION TNOM=val' for compatibility with HSPICE (DDIsa05531 - SMASH 5.15.0).
• Implemented handling of C-Logic models using the in-house Binary Simulation Model (BSM) technology (DDIsa05602 - SMASH 5.15.0).
• Implemented the support of semi-colon ';' as in-line comment character for the PSPICE flavor (DDIsa05769 - SMASH 5.15.0).
• Improved the DC extraction used by the FFT (DDIsa05774 - SMASH 5.15.0).
• Implemented a default temperature equal to 25 degC when the HSPICE flavor is selected (DDIsa05790 - SMASH 5.15.0).
• Accelerated the loading of flattened SPICE netlists (DDIsa05791 - SMASH 5.15.0).
• Added "lang=" option to the .LIB directive in order to allow specifying the hardware description language (DDIsa05895 - SMASH 5.15.0).
• September 30, 2010 Page 10/23SMASH 5.15.1, SCROOGE 2.4.1 & SHAKER 5.15.1 New Features
• Implemented improved SPICE parsing to accelerate parsing and provide better error reporting including file and line numbers (DDIsa01619 - SMASH 5.15.1).
• Improved convergence for some PSPICE models by improving detecting of non-finite (NaN) values during operating-point and transient analysis (DDIsa03199 - SMASH 5.15.1).
• Implemented SPICE parsing of .INCLUDE directives in sub-circuits for HSPICE compatibility (DDIsa04326 - SMASH 5.15.1).
• Implemented SPICE parsing of .LIB directives in sub-circuits for HSPICE compatibility (DDIsa05538 - SMASH 5.15.1).
• Implemented handling of per-circuit configuration preferences (DDIsa06035 - SMASH 5.15.1).
• Implemented the possibility to associate a Tcl script with a circuit to register circuit specific hook functions (DDIsa06098 - SMASH 5.15.1).
• Improved handling of simulator control file updates so that the original file is not damaged when there is no space left on disk (DDIsa06209 - SMASH 5.15.1).
• Modifications:
• Modified handling of analog simulations to stop simulations when waveform data can not be written to binary files, for
• instance when no disk space if available (DDIsa05907 - SMASH 5.15.0).
• Changed an error message to a warning message when the PowerUp convergence method fails during an operating-point analysis (DDIsa05980 - SMASH 5.15.0).
• Modified the limitations for the SPICE kit when using the Discovery option (DDIsa06011 - SMASH 5.15.0).
• Modified generation of operating-point file so that logic related data is not output by default and can be enabled through the application preferences (DDIsa05154 - SMASH 5.15.1).
• Modified handling of logic signals in a Verilog circuit hierarchy connecting SPICE sub-circuits to not create unnecessary interface devices (DDIsa05442 - SMASH 5.15.1).
• Modified the 'OP' parameter of directives '.AC' and '.NOISE' which should have the same default value (DDIsa06037 - SMASH 5.15.1).
• Modified handling of compiled logic descriptions so that the BSM intermediate files can be loaded when the Verilog source code is not available (DDIsa06186 - SMASH 5.15.1).
• Corrected embeddedWinelib to allow loading files with very long path names under Linux (DDIsa06193 - SMASH 5.15.1).
• Optimized handling of multiple blocking assigns on a signal in the same delta-cycle (DDIsa06281 - SMASH 5.15.1).
• Bug fixing:
• Corrected management of Spice to Verilog instantiation when passing Spice real parameters to Verilog integer parameters (DDIsa03293 - SMASH 5.15.0).
• Corrected the computation of analog power when SPICE devices are directly instantiated from Verilog-A (DDIsa05921 - SMASH 5.15.0).
• Corrected the operating-point file output when the device information selector is set to "ALL information" (DDIsa05923 - SMASH 5.15.0).
• Corrected a memory leak that occurred when closing a circuit with .PRINT and .PRINTALL directives in the simulator control file (DDIsa05946 - SMASH 5.15.0).
• Corrected VEC_WRITE which was appending data to the end of the VEC file when the simulation was run several times (DDIsa06007 - SMASH 5.15.0).
• Corrected a memory leak that occurred when closing a circuit with .MEASURE directives in the simulator control file (DDIsa06008 - SMASH 5.15.0).
• Corrected a memory deallocation error when a .LIB directive generates a parsing error that could cause SMASH to freeze (DDIsa06017 - SMASH 5.15.0).
• Corrected a crash that could occur during operating-point analysis of circuits with VHDL-AMS descriptions (DDIsa06021 - SMASH 5.15.0).
• Corrected VEC_READ verifications of analog templates which wrong when VOH and VOL values did not match VIH and VIL values (DDIsa06022 - SMASH 5.15.0).
• Corrected initialization of Laplace model function which could be incorrect during operating-point analysis (DDIsa06026 - SMASH 5.15.0).
• Corrected handling of unused nets in Verilog-A descriptions which created entries in the matrix and caused convergence problems (DDIsa05229 - SMASH 5.15.1).
• Corrected handling of TEMPER automatic parameter when running Sweep analyses (DDIsa05368 - SMASH 5.15.1).
• Corrected handling of the table function which crashed when 'x' values were not defined in increasing order (DDIsa05969 - SMASH 5.15.1).
• Corrected the Verilog-A laplace operator which could cause difficulties to find an operating-point (DDIsa06027 - SMASH 5.15.1).
• Corrected dependency handling of Verilog files included with the ‘include directive which were ignored by the dependency management (DDIsa06030 - SMASH 5.15.1).
• Corrected connection of logic signal to an analog port which was no longer creating an interface module (DDIsa06052 -SMASH 5.15.1).
• Correctedmeasurements on small-signal waveformfiles and added aliases formeasure directive file parameters (DDIsa06065 - SMASH 5.15.1).
• Corrected handling of .JITTER directive which was not being extracted after reloading circuit (DDIsa06080 - SMASH 5.15.1).
• Corrected a crash that could occur during initialization of a Verilog-A analog signal (DDIsa06097 - SMASH 5.15.1).
• Corrected handling of the VHDL-AMS DOMAIN signal which was not updated for small-signal analysis when an operatingpoint or transient analysis was run first (DDIsa06103 - SMASH 5.15.1).
• Corrected handling of the '.TRACE' directive which should not be case sensitive on waveform 'ONOISE' during a noise analysis (DDIsa06106 - SMASH 5.15.1).
• Features:
• Corrected generated of VCD files which could be incorrect when memories were traced (DDIsa06108 - SMASH 5.15.1).
• Corrected a crash that occurred when running a multiple operating-point analysis in batch mode and redirecting output to a
• file (DDIsa06161 - SMASH 5.15.1).
• Corrected saving of .FFT result file when "average" is enabled (DDIsa06171 - SMASH 5.15.1).
• Corrected SNR & THD computations when performed in a generic window from .FFT results file (DDIsa06192 - SMASH 5.15.1).
• Corrected generated ICD file name which was saved with an index off by one when running a Monte carlo analysis (DDIsa06211 - SMASH 5.15.1).
• Corrected display of an unexpected DC measure result file error message when running Sweep and Monte-Carlo analyses (DDIsa06234 - SMASH 5.15.1).
• Corrected handling of inline comments starting with the '$' character inside directives (DDIsa06235 - SMASH 5.15.1).
• Corrected handling of dependency between TEMPER parameter and .TEMP directive (DDIsa06245 - SMASH 5.15.1).
• Corrected SPICE sub-circuit instantiation from logic descriptions that could fail when instantiating multiple sub-circuits (DDIsa06248 - SMASH 5.15.1).
• Corrected waveform superposing which was disabled for logic simulations (DDIsa06258 - SMASH 5.15.1).
• Corrected the display of values in Tera (DDIsa06264 - SMASH 5.15.1).
• Corrected handling of circuit netlists with circular library dependencies found in some specific foundry library files which were causing a crash (DDIsa06276 - SMASH 5.15.1).
• SMASH - SPICE:
• Enhancements:
• Implemented support of directive '.OPTION TNOM=val' for compatibility with HSPICE (DDIsa05531 - SMASH 5.15.0).
• Implemented the support of semi-colon ';' as in-line comment character for the PSPICE flavor (DDIsa05769 - SMASH 5.15.0).
• Improved the DC extraction used by the FFT (DDIsa05774 - SMASH 5.15.0).
• Accelerated the loading of flattened SPICE netlists (DDIsa05791 - SMASH 5.15.0).
• Integrated SPICE device model PSP version 103.1 (DDIsa05936 - SMASH 5.15.0).
• Implemented improved SPICE parsing to accelerate parsing and provide better error reporting including file and line numbers (DDIsa01619 - SMASH 5.15.1).
• Improved convergence for some PSPICE models by improving detecting of non-finite (NaN) values during operating-point and transient analysis (DDIsa03199 - SMASH 5.15.1).
• Implemented SPICE parsing of .INCLUDE directives in sub-circuits for HSPICE compatibility (DDIsa04326 - SMASH 5.15.1).
• Implemented SPICE parsing of .LIB directives in sub-circuits for HSPICE compatibility (DDIsa05538 - SMASH 5.15.1).
• Implemented support for the different names that Verilog-AMS files constants.vams and disciplines.vams can have (DDIsa06152 - SMASH 5.15.1).
• Modifications:
• Modified handling of analog simulations to stop simulations when waveform data can not be written to binary files, for
• instance when no disk space if available (DDIsa05907 - SMASH 5.15.0).
• Changed an error message to a warning message when the PowerUp convergence method fails during an operating-point analysis (DDIsa05980 - SMASH 5.15.0).
• Modified handling of logic signals in a Verilog circuit hierarchy connecting SPICE sub-circuits to not create unnecessary interface devices (DDIsa05442 - SMASH 5.15.1).
• Modified the 'OP' parameter of directives '.AC' and '.NOISE' which should have the same default value (DDIsa06037 - SMASH 5.15.1).
• Modified handling of noise sources so that transient noise is not computed during power-up analysis (DDIsa06221 - SMASH 5.15.1).
• Bug fixing:
• Corrected management of Spice to Verilog instantiation when passing Spice real parameters to Verilog integer parameters (DDIsa03293 - SMASH 5.15.0).
• Corrected the computation of analog power when SPICE devices are directly instantiated from Verilog-A (DDIsa05921 - SMASH 5.15.0).
• Corrected the operating-point file output when the device information selector is set to "ALL information" (DDIsa05923 - SMASH 5.15.0).
• Corrected a memory leak that occurred when closing a circuit with .PRINT and .PRINTALL directives in the simulator control file (DDIsa05946 - SMASH 5.15.0).
• Corrected handling of TEMPER automatic parameter when running Sweep analyses (DDIsa05368 - SMASH 5.15.1).
• Corrected handling of the table function which crashed when 'x' values were not defined in increasing order (DDIsa05969 - SMASH 5.15.1).
• Correctedmeasurements on small-signal waveformfiles and added aliases formeasure directive file parameters (DDIsa06065 - SMASH 5.15.1).
• Corrected handling of .JITTER directive which was not being extracted after reloading circuit (DDIsa06080 - SMASH 5.15.1).
• Corrected the parsing of VNOISE source for parameters XSCALE and YSCALE and updated the documentation (DDIsa06090 - SMASH 5.15.1).
• Corrected handling of the '.TRACE' directive which should not be case sensitive on waveform 'ONOISE' during a noise analysis (DDIsa06106 - SMASH 5.15.1).
• September 30, 2010 Page 14/23SMASH 5.15.1, SCROOGE 2.4.1 & SHAKER 5.15.1 New Features
• Corrected parsing of bipolar model parameter TREF which was read in Kelvin instead of Celsius (DDIsa06137 - SMASH 5.15.1).
• Corrected a crash that occurred when running a multiple operating-point analysis in batch mode and redirecting output to a file (DDIsa06161 - SMASH 5.15.1).
• Corrected saving of .FFT result file when "average" is enabled (DDIsa06171 - SMASH 5.15.1).
• Corrected SNR & THD computations when performed in a generic window from .FFT results file (DDIsa06192 - SMASH 5.15.1).
• Corrected generated ICD file name which was saved with an index off by one when running a Monte carlo analysis(DDIsa06211 - SMASH 5.15.1).
• Corrected display of an unexpected DC measure result file error message when running Sweep and Monte-Carlo analyses (DDIsa06234 - SMASH 5.15.1).
• Corrected handling of inline comments starting with the '$' character inside directives (DDIsa06235 - SMASH 5.15.1).
• Corrected handling of dependency between TEMPER parameter and .TEMP directive (DDIsa06245 - SMASH 5.15.1).
• Corrected handling of UNIT=HERTZ parameter for polynomial descriptions in the Laplace model (DDIsa06255 - SMASH 5.15.1).
• Corrected handling of circuit netlists with circular library dependencies found in some specific foundry library files which were causing a crash (DDIsa06276 - SMASH 5.15.1).
• SMASH - Verilog & Verilog-AMS:
• Enhancements:
• Implemented support of Verilog-2001 parameter declarations with range specifications (DDIsa00671 - SMASH 5.15.0).
• Implemented management of Verilog "$dist_" system functions for probabilistic distributions (DDIsa01729 - SMASH 5.15.0).
• Implemented semantic verification for Verilog task enabling and values passed on arguments (DDIsa01769 - SMASH 5.15.0).
• Implemented semantic verification for Verilog task enabling and values passed on arguments (DDIsa01872 - SMASH 5.15.0).
• Implemented usage of integer, real, realtime and time expression types as arguments of Verilog user tasks and functions (DDIsa02157 - SMASH 5.15.0).
• Added static and dynamic detection of infinite loops in Verilog "always" and "forever" statements containing only nonblocking assignment statements (DDIsa02772 - SMASH 5.15.0).
• Implemented issuing of a warning message when using a real type value with %d format in Verilog $display system task (DDIsa02799 - SMASH 5.15.0).
• Implemented support of Verilog-2001 module port declarations in ANSI style (DDIsa03035 - SMASH 5.15.0).
• Implemented support of the Verilog-A Laplace analog operator (DDIsa03060 - SMASH 5.15.0).
• Implemented management of strength specifications in Verilog signal declarations (DDIsa03179 - SMASH 5.15.0).
• Implemented management of Verilog variable declarations in block statements (DDIsa03243 - SMASH 5.15.0).
• Improved the Verilog parsing error messages when enabling an undeclared user function (DDIsa03300 - SMASH 5.15.0).
• Implemented support of Verilog-2001 "localparam" declarations (DDIsa03302 - SMASH 5.15.0).
• Implemented management of Verilog variable declarations in sequential and parallel block statements (DDIsa03358 - SMASH 5.15.0).
• Implemented issuing a warning message when Verilog UDP contains conflicting table entries (DDIsa03473 - SMASH 5.15.0).
• Implemented handling of Verilog (non-)blocking assignments with intra delays in named block statements (DDIsa03649 - SMASH 5.15.0).
• Improved the compilation runtime when declaring and using several Verilog user tasks (DDIsa03780 - SMASH 5.15.0).
• Implemented support of Verilog-2001 "@*" statements (DDIsa03845 - SMASH 5.15.0).
• Implemented management of concatenation expressions with constant values which are passed to Verilog task or function arguments (DDIsa03872 - SMASH 5.15.0).
• Implemented support of Verilog "@(event expression)" when expression contains operators (DDIsa04093 - SMASH 5.15.0).
• Implemented handling of Verilog "‘timescale" directives with "10s" and "100s" units (DDIsa04112 - SMASH 5.15.0).
• Improved error message issued when compiling and elaborating Verilog models (DDIsa04173 - SMASH 5.15.0).
• Implemented static and dynamic detection of infinite loops in Verilog "forever" statements (DDIsa04253 - SMASH 5.15.0).
• Implemented Verilog instantiation of gate arrays where a connection is a scalar signal (DDIsa04689 - SMASH 5.15.0).
• Upgraded the embedded Verilog parser to pave the way for Verilog 2001, Verilog-AMS 2.3, and SystemVerilog (DDIsa04784 - SMASH 5.15.0).
• Implemented handling during simulation of delay value changes in Verilog continuous assignment statements (DDIsa04799 - SMASH 5.15.0).
• Implemented support of bit-selection and part-selection on Verilog "integer" variables in left-hand side expression contexts (DDIsa04853 - SMASH 5.15.0).
• Implemented support of bit-selection and part-selection on Verilog "time" variables in left-hand side expression contexts (DDIsa04854 - SMASH 5.15.0).
• Implemented support of Verilog port declarations with "tri0" or "tri1" net-types (DDIsa04979 - SMASH 5.15.0).
• Implemented handling of different but compatible data types for expressions passed to Verilog function arguments (DDIsa05053 - SMASH 5.15.0).
• Improved Verilog error messages when connection mismatches occur during elaboration (DDIsa05640 - SMASH 5.15.0).
• Implemented handling of Verilog $stop and $finish system tasks as function statements (DDIsa05743 - SMASH 5.15.0).
• Features:
• Implemented handling of Verilog signal part-selections as actual connections on output ports (DDIsa05748 - SMASH 5.15.0).
• Implemented SDF annotation handling on Verilog "$setuphold" with negative "setup" or "hold" values (DDIsa05947 - SMASH 5.15.0).
• Implemented handling in Verilog-A of multiple analog blocks (DDIsa05984 - SMASH 5.15.0).
• Implemented issuing an error message when using a Verilog electrical port as left-hand-side of continuous assignment statement (DDIsa05997 - SMASH 5.15.0).
• Implemented support of 'signed' keyword in Verilog register declarations (DDIsa03766 - SMASH 5.15.1).
• Implemented support for Verilog delay annotation using compressed (gzip) SDF files (DDIsa05504 - SMASH 5.15.1).
• Implemented support for Verilog PATHPULSE$ parameters with rejection limit (DDIsa06094 - SMASH 5.15.1).
• Improved handling of multi-threading for Verilog-AMS analog descriptions (DDIsa06200 - SMASH 5.15.1).
• Modifications:
• Removed limitation to 32 bits on Verilog parameter values for binary, octal and hexadecimal literals (DDIsa01718 - SMASH 5.15.0).
• Modified Verilog display of time value which was limited to 32 bits and which now allows 64 bit values (DDIsa02841 - SMASH 5.15.0).
• Modified Verilog task portsmanagement to behave like Verilog task variable with respect to the "automatic" style (DDIsa03960 - SMASH 5.15.0).
• Modified compilation handling of Verilog models with a large (such as 2000) number of parameter declarations which previously failed to compile (DDIsa04122 - SMASH 5.15.0).
• Modified compilation handling of Verilog models with large (such as 200000) number of statements in "initial" or "always"
• blocks which previously failed to compile (DDIsa04525 - SMASH 5.15.0).
• Modified handling of Verilog model libraries so that invalid or not yet supported models do not prevent using other models (DDIsa05604 - SMASH 5.15.0).
• Modified Verilog messages so that the source code position where the error occurs can be displayed with clickable links (DDIsa05944 - SMASH 5.15.0).
• Modified generation of operating-point file so that logic related data is not output by default and can be enabled through the application preferences (DDIsa05154 - SMASH 5.15.1).
• Modified handling of logic signals in a Verilog circuit hierarchy connecting SPICE sub-circuits to not create unnecessary interface devices (DDIsa05442 - SMASH 5.15.1).
• Extended use of Verilog mintypmax expressions so that they are not restricted to the values of parameters (DDIsa06029 - SMASH 5.15.1).
• Added missing source link in error message issued to report file when declaring several Verilog variables/wires with the same name (DDIsa06040 - SMASH 5.15.1).
• Page 17/23 September 30, 2010New Features SMASH 5.15.1, SCROOGE 2.4.1 & SHAKER 5.15.1
• Modified handling of warning concerning the use of the default Verilog timescale so that it is issued only when the timescale is used by the module (DDIsa06050 - SMASH 5.15.1).
• Modified handling of compiled logic descriptions so that the BSM intermediate files can be loaded when the Verilog source code is not available (DDIsa06186 - SMASH 5.15.1).
• Improved Verilog error messages in case of unknown system functions, not supported system functions and not supported call styles (DDIsa06188 - SMASH 5.15.1).
• Optimized handling of multiple blocking assigns on a signal in the same delta-cycle (DDIsa06281 - SMASH 5.15.1).
• Bug fixing:
• Corrected a crash that occurred when a Verilog scalarmodule input declaration was redeclared as a vector wire (DDIsa02987 - SMASH 5.15.0).
• Corrected the checking in Verilog-A of mathematical operand types (DDIsa03019 - SMASH 5.15.0).
• Corrected handling of forward declarations of Verilog signals (DDIsa03068 - SMASH 5.15.0).
• Corrected support in Verilog-A of infinite values inside parameter range specifications (DDIsa03251 - SMASH 5.15.0).
• Corrected management of Spice to Verilog instantiation when passing Spice real parameters to Verilog integer parameters (DDIsa03293 - SMASH 5.15.0).
• Corrected handling of Verilog constant value 2147483648 which previously failed to compile (DDIsa03746 - SMASH 5.15.0).
• Corrected a crash that could occur due to an uncaught exception in a Verilog model (DDIsa03931 - SMASH 5.15.0).
• Corrected a compilation error when a Verilog task output argument is passed to a sub-task enabling (DDIsa03963 - SMASH 5.15.0).
• Corrected handling of coverage analysis with Verilog expressions containing logic and real arguments (DDIsa05199 - SMASH 5.15.0).
• Corrected evaluation of Verilog replication expressions where the constant is zero (DDIsa05227 - SMASH 5.15.0).
• Corrected handling of forward declarations of Verilog variables (DDIsa05232 - SMASH 5.15.0).
• Corrected a crash that occured in Verilog-A when using an input array in an analog function (DDIsa05431 - SMASH 5.15.0).
• Corrected handling of negative values for Verilog port ranges (DDIsa05520 - SMASH 5.15.0).
• Corrected the computation of analog power when SPICE devices are directly instantiated from Verilog-A (DDIsa05921 - SMASH 5.15.0).
• Corrected assignment of Verilog real parameters to VHDL integer generics where the value was truncated instead of rounded (DDIsa05948 - SMASH 5.15.0).
• Corrected behavior of Verilog MOS switches so that they propagate the input strength changes even if no level edge occurs (DDIsa05949 - SMASH 5.15.0).
• Features:
• Corrected behavior of Verilog "$hold" and "$recovery" timing-check functions which could report wrong violations at simulation initialization (DDIsa05993 - SMASH 5.15.0).
• Corrected the name of SPICE primitives isine and vsine that were not loaded as described in the LRM (DDIsa06009 - SMASH 5.15.0).
• Corrected initialization of Laplace model function which could be incorrect during operating-point analysis (DDIsa06026 - SMASH 5.15.0).
• Corrected triggering of sensitivity on Verilog variables assigned several times in a single delta-cycle (DDIsa04932 - SMASH 5.15.1).
• Corrected handling of unused nets in Verilog-A descriptions which created entries in the matrix and caused convergence problems (DDIsa05229 - SMASH 5.15.1).
• Corrected the Verilog-A laplace operator which could cause difficulties to find an operating-point (DDIsa06027 - SMASH 5.15.1).
• Corrected dependency handling of Verilog files included with the ‘include directive which were ignored by the dependency management (DDIsa06030 - SMASH 5.15.1).
• Corrected a crash that could occur when loading and running numerous Verilog circuits in a single instance of SMASH (DDIsa06033 - SMASH 5.15.1).
• Corrected a crash that could occur when initializing a Verilog-A analog variable (DDIsa06042 - SMASH 5.15.1).
• Corrected connection of logic signal to an analog port which was no longer creating an interface module (DDIsa06052 - SMASH 5.15.1).
• Corrected a crash that could occur during initialization of a Verilog-A analog signal (DDIsa06097 - SMASH 5.15.1).
• Corrected a crash that occurred for Verilog replications on literals with a 0 replication constant value (DDIsa06101 - SMASH 5.15.1).
• Corrected handling of parameters used in replication constants which could cause circuit loading to fail (DDIsa06102 - SMASH 5.15.1).
• Corrected generated of VCD files which could be incorrect when memories were traced (DDIsa06108 - SMASH 5.15.1).
• Corrected handling of Verilogmodule path conditions which were ignored when using previously compiledmodels (DDIsa06109 - SMASH 5.15.1).
• Corrected access to logic array variables inside Verilog analog blocks (DDIsa06111 - SMASH 5.15.1).
• Corrected handling of Verilog-A variables with an unknown domain which were causing aminimumtime step (DDIsa06115 - SMASH 5.15.1).
• Corrected a crash that occurred when connecting an analog real variable to a port (DDIsa06119 - SMASH 5.15.1).
• Corrected handling of integer used in $realtobits Verilog conversion function which was raising an error (DDIsa06122 - SMASH 5.15.1).
• Corrected handling of the $display Verilog system task which was outputing a wrong string when several %t format speci- fiers were used (DDIsa06160 - SMASH 5.15.1).
• Corrected code generation for Verilog sized literals (1'b0) used in analog expressions (DDIsa06164 - SMASH 5.15.1).
• Corrected a crash that occurred in Verilog non blocking assignments with out-of-bounds bit selections (DDIsa06166 - SMASH 5.15.1).
• Corrected handling of Verilog $sdf_annotate system task calls so that hierarchical names are accepted for the second argument (DDIsa06173 - SMASH 5.15.1).
• Corrected handling of Verilog-A derivative computation of mathematical function in some cases which could cause convergence issues (DDIsa06190 - SMASH 5.15.1).
• Corrected signal rejection handling where Verilog wire pulses were no longer rejected (DDIsa06191 - SMASH 5.15.1).
• Corrected a memory leak that occured during code generation of Verilog-AMS descriptions (DDIsa06204 - SMASH 5.15.1).
• Corrected Verilog timing checks which did not catch event on the signals after 4us (DDIsa06268 - SMASH 5.15.1).
• Corrected handling of "{$random}%int" which produces a positive number (DDIsa06271 - SMASH 5.15.1).
• Corrected sequential UDP behavior when the output port is delayed by a module path (DDIsa06272 - SMASH 5.15.1).
• SMASH - VHDL & VHDL-AMS:
• Improvements:
• Added support for '-I' and '-L' options in the VHDL FOREIGN attribute to specify the search paths respectively to include
• and library files (DDIsa06010 - SMASH 5.15.0).
• Modifications:
• Modified generation of operating-point file so that logic related data is not output by default and can be enabled through the application preferences (DDIsa05154 - SMASH 5.15.1).
• Bug fixing:
• Corrected behavior of the VHDL return statement when returning a slice (DDIsa05990 - SMASH 5.15.0).
• Corrected a crash that could occur during operating-point analysis of circuits with VHDL-AMS descriptions (DDIsa06021 - SMASH 5.15.0).
• Corrected initialization of Laplace model function which could be incorrect during operating-point analysis (DDIsa06026 - SMASH 5.15.0).
• Corrected handling of the VHDL-AMS DOMAIN signal which was not updated for small-signal analysis when an operatingpoint or transient analysis was run first (DDIsa06103 - SMASH 5.15.1).
• Corrected implementation of VHDL TEXTIO LINE type where a READ or WRITE with a copied LINE variable could crash SMASH (DDIsa06198 - SMASH 5.15.1).
• Corrected the implementation of VHDL TEXTIO.READ(LINE, STRING) so that it does not skip leading whitespace characters (DDIsa06223 - SMASH 5.15.1).
• Features:
• Corrected implementation of IEEE.STD_LOGIC_TEXTIO.HREAD which could fail and emit "invalid array" error messages (DDIsa06275 - SMASH 5.15.1).
• SMASH - PSL:
• Bug fixing:
• Corrected simulation models generated for PSL properties that could not be compiled under Linux (DDIsa06110 - SMASH 5.15.1).
• Corrected assertion inputs sampling which must be performed in the preponed region and corrected handling of PSL SEREs that cannot be or are always matched (DDIsa06260 - SMASH 5.15.1).
• SMASH - Models (C, D, E, F, G, H, I, J, K, L, M, Q, R, T, U, V):
• Enhancements:
• Integrated SPICE device model PSP version 103.1 (DDIsa05936 - SMASH 5.15.0).
• Implemented support of correlation parameters in the MNOISE model (DDIsa06107 - SMASH 5.15.1).
• Modifications:
• Modified handling of noise sources so that transient noise is not computed during power-up analysis (DDIsa06221 - SMASH 5.15.1).
• Bug fixing:
• Corrected BSIM4 model to take scaling factor into account to compute conductance of parasitic resistors (DDIsa05975 - SMASH 5.15.0).
• Corrected VEC_WRITE which was appending data to the end of the VEC file when the simulation was run several times (DDIsa06007 - SMASH 5.15.0).
• Corrected VEC_READ verifications of analog templates which wrong when VOH and VOL values did not match VIH and VIL values (DDIsa06022 - SMASH 5.15.0).
• Corrected initialization of Laplace model function which could be incorrect during operating-point analysis (DDIsa06026 - SMASH 5.15.0).
• Corrected the parsing of VNOISE source for parameters XSCALE and YSCALE and updated the documentation (DDIsa06090 - SMASH 5.15.1).
• Corrected parsing of bipolar model parameter TREF which was read in Kelvin instead of Celsius (DDIsa06137 - SMASH 5.15.1).
• Corrected handling of UNIT=HERTZ parameter for polynomial descriptions in the Laplace model (DDIsa06255 - SMASH 5.15.1).
• SMASH - SDF:
• Enhancements:
• Implemented SDF annotation handling on Verilog "$setuphold" with negative "setup" or "hold" values (DDIsa05947 - SMASH 5.15.0).
• Implemented support for Verilog delay annotation using compressed (gzip) SDF files (DDIsa05504 - SMASH 5.15.1).
• Bug fixing:
• Corrected the SDF annotation of an IOPATH with the RETAIN keyword so that it is annotated without the RETAIN which is not yet supported (DDIsa05977 - SMASH 5.15.0).
• Corrected matching between Verilog and SDF for escaped identifiers starting with a double backslash (DDIsa06068 - SMASH 5.15.1).
• Corrected handling of Verilog $sdf_annotate system task calls so that hierarchical names are accepted for the second argument (DDIsa06173 - SMASH 5.15.1).
• SMASH - Licensing:
• Modifications:
• Modified the limitations for the SPICE kit when using the Discovery option (DDIsa06011 - SMASH 5.15.0).
• SCROOGE - Viewer:
• Bug fixing:
• Corrected management of escaped identifiers so that the instance hierarchy tree is correctly displayed in the Powermap (DDIsa06168 - SCROOGE 2.4.1).
• Corrected handling of the power average extraction dialog fields which could not be validated under Unix (DDIsa06252 - SCROOGE 2.4.1).
• SCROOGE - Kernel:
• Enhancements:
• Implemented AQD(t) accumulative charge deficit extraction of maximum peak charge (DDIsa06064 - SCROOGE 2.4.1).
• Modifications:
• Modified handling of the SPEF annotation so that the internal binary file is generated in the -smash subdirectory (DDIsa05991 - SCROOGE 2.4.0).
• Features:
• Modified handling of Liberty "related_pin" attributes in "timing" groups so that they are no longer mandatory (DDIsa06013- SCROOGE 2.4.0).
• Bug fixing:
• Corrected $scrooge_get_current API function which was no longer available for power consumption behavioral modeling (DDIsa06150 - SCROOGE 2.4.1).
• Corrected handling of spaces in paths for SPEF files so that the files can be compiled by SCROOGE (DDIsa06195 - SCROOGE 2.4.1).
• DOCUMENTATION:
• Modifications:
• Added to the SMASH Reference Manual a summary table of all SPICE-like device/model types available (DDIsa05115 - SMASH 5.15.0).
• Bug fixing:
• Corrected the SMASH Reference Manual documentation of poly capacitor behavior (DDIsa05956 - SMASH 5.15.0).
• Corrected SHAKER extraction of CCS Power segmentation which was duplicating some extracted points (DDIsa06105 -SHAKER 5.15.1).
• COSMOS:
• Modifications:
• Modified end of simulation handling in the COSMOS interface with MATLAB so that SMASH traces extend to the simulation end time of Simulink (DDIsa06004 - SMASH 5.15.0).
• Bug fixing:
• Corrected an issue in the COSMOS interface with MATLAB that could crash at the end of the simulation (DDIsa05999 -SMASH 5.15.0).
• Corrected an issue in the COSMOS interface with MATLAB that no longer correctly connected SPICE nets (DDIsa06001- SMASH 5.15.0

What is new in version 5.15.0:

• This version implements analog equivalence checking with measures and template checking on waveforms (transient, FFT, small-signal, Jitter, etc.), improved compliance with Verilog standards, increased circuit size capacity for Verilog and Verilog-A descriptions (including Compact Models), accelerated circuit loading and transient simulation of Verilog and Verilog-A models, increased compatibility with HSpice foundry files using the GEOSHRINK directive for device dimension scaling, and increased circuit size capacity for SPICE when using statistical foundry models.